1. Field of the Invention
The present invention relates to content addressable memory (CAM) cells. More specifically, the present invention relates to nine transistor CAM cells and methods for operating these cells in an array.
2. Discussion of Related Art
CAM cells are defined as memory cells that are addressed in response to their content, rather than by a physical address within an array. FIG. 1 is a block diagram of a conventional memory array formed using twelve CAM cells. The CAM cells are labeled MX,Y, where X is the row of the array, and Y is the column of the array. Thus, the array includes CAM cells M0,0 to M2,3. Each of the CAM cells is programmed to store a data value. In the described example, the data value stored in each CAM cell is indicated by either a “0” or a “1” in brackets. For example, CAM cells M0,0, M0,1, M0,2 and M0,3 store data values of 0, 1, 0 and 0, respectively. Each row of CAM cells is coupled to a common match line. For example, CAM cells M0,0, M0,1, M0,2 and M0,3 are coupled to match line MATCH0.
The array of CAM cells is addressed by providing a data value to each column of CAM cells. Thus data values D0, D1, D2 and D3 are provided to columns 0, 1, 2 and 3, respectively. Note that complementary data values D0#, D1#, D2# and D3# are also provided to columns 0, 1, 2 and 3, respectively. If the data values stored in a row of the CAM cells match the applied data values D0-D3, then a match condition occurs. For example, if the data values D0, D1, D2 and D3 are 0, 1, 0 and 0, respectively, then the data values stored in the CAM cells of row 0 match the applied data values. Under these conditions, the MATCHo signal is asserted high. Because the applied data values D0, D1, D2 and D3 do not match the data values store in the CAM cells of rows 1 or 2, the MATCH1 and MATCH2 signals are de-asserted low. The match signals Match0-MATCH2 can be used for various purposes, such as implementing virtual addressing, in a manner (known to those skilled in the art.
Many different types of CAM cells have been designed. Important considerations in the design of a CAM cell include: the number of transistors required to implement the cell, the power required to operate the CAM cell, and the speed of the CAM cell. In general, it is desirable to have a CAM cell that is implemented using a relatively small number of transistors, such that the layout area of the CAM cell is minimized. It is also desirable for the CAM cell to have a low power requirement and a fast operating speed.
FIG. 2 is a circuit diagram of a conventional nine tune transistor (9-T) CAM cell 10. CAM cell 10 is described in detail in U.S. Pat. No. 4,723,224. CAM cell 10 includes a conventional static random access memory (SRAM) cell 12 and as exclusive OR (XOR) gate 14. SRAM cell 12 includes access transistors 20 and 22, and cross-coupled inverters 16 and 18. Access transistors 20 and 22 are coupled to word line 28 and bit lines 24 and 26, as illustrated. Driver circuitry 36 provides a data value (D) and the inverse of the data value (D#) to bit lines 24 and 26, respectively, during write and compare operations.
SRAM cell 12 is written like a conventional SRAM cell. That is, a logic high value is applied to word line 28, and data values D and D# are applied to bit lines 24 and 26, respectively. As a result, the data values D and D# are latched by inverters 16 and 18, such that the data value D is provided as the output of inverter 18, and the inverted data value D# is provided at the output of inverter 16.
XOR gate 14 includes n-channel transistors 30 and 32, which are connected in series between bit lines 24 and 26. The output terminal of inverter 16 is connected to the gate of transistor 30, such that the inverted data value D# stored in SRAM cell 12 is provided to the gate of transistor 30. Similarly, the output terminal of inverter 18 is connected to the gate of transistor 32, such that the data value D stored in SRAM cell 12 is provided to the gate of transistor 30. Transistors 30 and 32 are commonly connected at node 34, which forms the output terminal of XOR gate 14. Node 34 is connected to the gate of n-channel transistor 38. Transistor 38 has a source coupled to ground line 42, and a drain coupled to match line 40.
CAM cell 10 performs a compare operation as follows. Driver circuitry 36 applies a comparison data value (C) and its complement (C#) to bit lines 24 and 26, respectively. If the comparison data value C matches the data value D stored in SRAM cell 12, then node 34 is connected to receive a logic “0” signal. As a result, transistor 38 is turned off, thereby isolating match line 40 from ground line 42. Under these conditions, match line 40 retains a pre-charged logic high value.
Conversely, if the comparison data value C does not match the data value D stored in SRAM cell 12, then node 34 is connected to receive a logic “1” signal. As a result, transistor 38 is turned on, thereby coupling match line 40 to ground line 42. Under these conditions, match line 40 is pulled down toward ground.
CAM cell 10 exhibits relatively high power consumption because the same driver circuitry 36 is used to supply the write data values as well as the comparison data values. Driver circuitry 36 is powered by the VCC supply voltage, such that both the write and comparison data values have logic high values of VCC. Moreover, the compare operation of CAM cell 10 is relatively slow because the capacitance of SRAM cell 12 is coupled to bit lines 24 and 26 during the compare operation.
It would therefore be desirable to have an improved CAM cell which allows a compare operation to be carried out using a supply voltage less than the VCC supply voltage. It would also be desirable for the improved CAM cell to have bit lines that are not coupled to the capacitance introduced by an SRAM cell during a compare operation. It would also be desirable for the improved CAM cell to be implemented using fewer transistors than conventional CAM cell 10. It would further be desirable for the improved CAM cell to have global and local masking capabilities.